The present invention relates to a semiconductor memory system using a DRAM or the like which can realize a high speed access.
A DRAM has been developed in integration to the highest level among MOS semiconductor memories because of the simplicity of a memory cell in a comparative sense and is now used as a main memory of all kinds of computer based apparatuses. On the other hand, there has been progress to in improving memory performance being driven by the rapid increase in capabilities of a microprocessor (MPU) in recent years: various kinds of DRAMs each provided with a high speed data cycle function have been proposed and some are already in early stages of mass production. Typical examples are the so-called synchronous DRAM (SDRAM) in which all I/O data are stored or retrieved in synchronism with a system clock and a double-data-rate SDRAM (DDR-SDRAM) which makes it possible to use both edges of a clock pulse as triggers for access though similar to the former in terms of operation, and the like. In addition to the above described DRAMs, a RAMBUS DRAM (RDRAM) (under specifications of Rambus Inc.) in which data transfer is enabled at a high speed with a protocol-based command, and the like have also been developed and a trend in which a conventional asynchronous DRAM is replaced with a synchronous DRAM can be assured to be a necessity in the future.
A characteristic of such a synchronous DRAM is that the maximal bandwidth is operated at a very high speed. As the maximal bandwidth of the latest SDRAM versions, for example, 100 Mbps has been achieved. A DDR-SDRAM and a R-DRAM are estimated to reach 200 Mbps and 800 Mbps respectively in the future. Such a high bandwidth, however, is realized only in burst access along a limited, specific row direction in a memory space. That is, a speed in a so-called random access operation in which a row address is changed can be attained only on almost the same order as a conventional asynchronous DRAM.
A hierarchical structure of a memory has been adopted as a general measure to cope with this situation in a computer system which adopts a DRAM as the main memory. In a concrete manner, the measure is that a cache memory which is constructed from an SDRAM which can realize a high speed access as compared with a DRAM is interposed between a MPU and the DRAM and data of part of the DRAM is cached in the SDRAM. In this case, a memory access from the MPU is performed or the high speed cache memory, and only when an access instruction enters an address space which is not cached in the cache memory, that is, when a cache miss occurs, an access is performed on the DRAM. A great improvement of a computer performance has been realized by adopting this measure even when operating speeds of the MPU and the DRAM are different from each other.
When a cache miss has occurs, however, read-out from the DRAM comes to be required and especially when a different row address in the same block in the DRAM memory space is accessed, there arises the maximal wait time for the MPU. This problem will be described with reference to FIG. 14 below.
FIG. 14 shows an example of a read operation timing for an SDRAM. When a cache miss occurs in the above described computer system which adopts a hierarchical structure of memory and a necessity of access to an SDRAM as a main memory arises, a [precharge command (Precharge)] is issued to perform precharge to an address which is now activated from the system side at time t1. Subsequently, an [activate command (Active)] is issued from the MPU after a predetermined time has elapsed and a bank corresponding to a necessary memory space is activated. A [read command (Read)] is issued after another specific time elapsed. Data of a specific burst length is read out from the SDRAM in synchronism with a clock pulse at a time t2 when a specific time has elapsed after the issuance of the read command. As shown here, the maximal bandwidth when a read operation is successively performed synchronously with a clock pulse is very high, whereas an effective bandwidth for random access in a cache miss is greatly decreased. That is, it is found that a portion of the time period between the time t1 and the t2 when no data is read out, in other words a wait time as viewed from the MPU side, is long.
In a concrete manner, in the case of the specifications of an SDRAM shown in FIG. 14, the maximal bandwidth in a random access cycle is of the order of 36% of that in a burst cycle at most. There will arise a high possibility for this to be a bottle neck in improving computer performance and therefore, the demand for a high performance DRAM has been increasing in which a high access time and a high speed cycle time are realized. Especially, in a multi-MPU system to which a current high-performance server machine is central, high importance is attached to not only high-speed burst transfer but high speed random access. Besides, in a consumer multi-media system in which real time reproduction of a dynamic image is the main object in the future, as well, a DRAM in which a high-speed random access is enabled in a similar way is considered to be a requirement.
With such demands in the backgrounds, an Enhanced SDRAM (ESDRAM) which has been announced from Enhanced Memory Systems Inc., as shown in FIG. 15, a Virtual Channel Memory (VCM) which has been announced from NEC Corp., as shown in FIG. 16, and the like have been proposed.
As described above, a DRAM, in which a high speed data cycle has been realized; represented by an SDRAM, an RDRAM and the like, suffers a long wait time when an access hit miss requires a random access occur, which is a problem causing a bottle neck in performance improvement of a system.
In the methods of FIGS. 15 and 16, in each of which a large capacity cache memory is provided in order to realize a high speed access time and a high speed cycle time, the overhead for a chip size is high, which in turn causes a problem that realization of the low cost is harder to achieve.